1. Technical Field
The present invention relates to registration mark such as an alignment or overlay mark, and more specifically, to methods of forming a registration mark during sidewall image transfer for sub-lithographic structure formation, and the resulting semiconductor structure.
2. Related Art
Photolithography is a technique for transferring an image rendered on one media onto another media photographically. Photolithography techniques are widely used in semiconductor fabrication. Typically, a circuit pattern is rendered as a positive or negative mask image which is then projected onto a silicon substrate coated with photosensitive materials (e.g., PR). Radiation impinges on the masked surface to chemically change those areas of the coating exposed to the radiation, usually by polymerizing the exposed coating. The un-polymerized areas are removed, being more soluble in the developer than the polymerized regions, and the desired image pattern remains.
In the microelectronics industry as well as in other industries involving construction of microscopic structures (e.g., micromachines, magnetoresistive heads, etc.) there is a continued desire to reduce the size of structural features and microelectronic devices and/or to provide a greater amount of circuitry for a given chip size. Miniaturization in general allows for increased performance (more processing per clock cycle and less heat generated) at lower power levels and lower cost. Present technology is at atomic level scaling of certain micro-devices such as logic gates, FETs and capacitors, for example. Circuit chips with hundreds of millions of such devices are common.
In order to achieve further size reductions exceeding the physical limits of trace lines and micro-devices that are embedded upon and within their semiconductor substrates, techniques that exceed lithographic capabilities have been employed. Sidewall image transfer (SIT), also known as self-aligned double patterning (SADP), is one such technique to generate sub-lithographic structures. SIT involves the usage of a sacrificial structure (e.g., a mandrel, typically composed of a polycrystalline silicon), and a sidewall spacer (such as silicon dioxide or silicon nitride, for example) having a thickness less than that permitted by the current lithographic ground rules formed on the sides of the mandrel (e.g., via oxidization or film deposition and etching). After removal of the mandrel, the remaining sidewall spacer is used as a hard mask (UM) to etch the layer(s) below, for example, with a directional reactive ion etch (RIE). Since the sidewall spacer has a sub-lithographic width (less than lithography allows), the structure formed in the layer below will also have a sub-lithographic width. In addition, side wall spacer at both side of sacrificial structure doubles patter density, resulting in final pitch half of the original sacrificial pattern pitch.
One challenge created by the creation of sub-lithographic structures using SIT is creating proper registration marks such as alignment and overlay marks. The requirement to ensure alignment of tools and/or proper overlay of successive patterned layers on a semiconductor wafer during fabrication are two of the most important processes in the manufacture of integrated circuits. Overlay marks are used to ensure overlay accuracy during IC manufacture. Overlay precision relates to the determination of how precise a first patterned layer aligns with a successive patterned layer positioned below or above the first layer, and how well the patterns align. Alignment marks are used to align different tools, such as reticles, to the semiconductor wafer. Conventionally, registration marks such as alignment and overlay marks are created with the layers of the wafer. In particular, a registration mark could be drawn in relatively large planar slab to create a good quality signal for mark identifying equipment. With SIT processes, however, to achieve a maximum density of material, designs must be at a minimum pitch and orientation, which limits the availability of structures that can be generated. Consequently, creation of registration marks during SIT processes that have good contrast and/or are capable of creating a good quality signal, especially outside of minimum design size, is challenging.